1. Field of the Invention
This invention relates to a semiconductor memory circuit device such as a random access memory (RAM) constituted by basic cells formed on a semiconductor substrate according to the Master slice approach, and more particularly to a semiconductor memory circuit device in which time for data readout is reduced.
2. Description of the Related Art
In general, the master slice approach is known as a technique of forming an integrated circuit on a semiconductor substrate.
With the Master slice approach, basic cells corresponding to logic gates such as NAND gates or NOR gates are first formed on the semiconductor substrate in a matrix form, for example. After this, wirings are formed to interconnect the basic cells so as to form an integrated circuit according to the purpose of application thereof.
The integrated circuit formed by use of the Master slice approach includes a gate array type integrated circuit. The gate array type circuit may be used in CMOS gate arrays to constitute random access memories (which are hereinafter referred to as RAMs).
The RAMs constituted by use of CMOS arrays generally include write-in drivers, a plurality of memory sections constituting memory cells, readout inverters and the like, and the RAMs are connected to at least one input line and at least one output line.
That is, write-in data is written into at least one memory cell via the input line. The write-in data is read out from the memory cell in response to a readout signal and output via the output line. A value of a potential level corresponding to the data held in the memory section is output via the output line by means of the readout inverter as the readout data output from the output stage of the memory cell.
Thus, since the output line is driven according to the potential level of the readout data output from the output stage of each memory cell, the whole readout time of the RAMs is determined by the driving ability of the output stage of each memory cell.
In general, in order to reduce the readout time, it may be effective to enhance the driving ability of the output stage by changing the dimensions of the element constituting the memory cell. However, as described before, since the gate array type memory cell is an integrated circuit which is formed by interconnecting previously formed circuit elements, it becomes impossible to form the individual RAMs by use of elements having proper dimensions so as to meet the purpose of application.
As a result, if a large number of memory cells are connected to one output of memory cell, the potential level of data output from the output stage of the RAM becomes low speed and is not high speed enough to drive the output line. Therefore, it is difficult to operate the memory cells at a high speed operation and reduce the readout time of the RAMs.